TimingExplorer is a physically-aware, multi-corner, multi-mode timing ECO tool for rapidly achieving timing closure in nanometer-scale IC designs.
Physically-aware capability allows TimingExplorer to account for effects such as congestion and routing topology while making ECO, and the ability to directly read the timing graph from STA tools avoids differences introduce with re-calculating timing. The result is a great speed-up in processing and an acceleration in timing convergence.
Designed to augment existing tools and flows, TimingExplorer has been used in production for over 6 years. It gives the fastest convergence of any tool available, and produces very high-quality layouts.
Key Benefits:
Reduces number of iterations through ECO cycle
Reduces time through each iteration
Achieves sign-off time correlation and layout correlation
Key Features:
Fix hold, setup, max transistion and max cap violations
