ICExplorer-XTop is a genuine placement- and routing-aware, multi-corner, multi-mode timing ECO solution with minimal impact to power and area in nanometer-scale IC designs.
Timing closure is a major problem with today’s SOC designs impacting time to market, revenue, and cost of design. It gets worse with each new process node. ICExplorer-XTop helps design teams to achieve faster timing /ECO closure and complements existing place and route and sign-off static timing analysis STA (Static Timing Analysis) tools in a user’s flow.
ICExplorer-XTop has been used in production for over a decade. It provides much faster timing closure convergence than conventional timing ECO flows.
•Fix large number of violations (> 50k) fast
•Accelerate timing closure process
•Cut down ECO iterations to 2-4
•Advanced process node proven down to 7nm
•Handle more than 300+ MMMC scenarios in one session
•Silicon correlated timing signoff for better PPA and yield, for designs with 100M+ instances, 300+ scenarios, and 100+ critical paths
•Placement aware and routing aware timing ECO with high P&R correlation
•Simultaneous and fast MMMC timing fixing on signal and clock paths
•Fix setup, hold, max transition/capacitance and SI violations
•Timing debug / interactive manual ECO
•Supports physical hierarchy and multi-power/voltage domains
•Plugin-and-play with existing flows using standard interfaces