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ICExplorer Overview |
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ICExplorer is a physical design, optimization, and verification tool suite for deep sub-micron IC designs. The objective of ICExplorer is to provide non-existing solutions or more efficient alternative solutions to complex design clock and timing problems.
ICExplorer consists of series of satellite tools, DBExplorer, ClockExplorer, TimingExplorer, and LibExplorer. DBExplorer analyzes the design data and hyperlinks them such that user can easily browse the design data by search and cross-probing. ClockExplorer helps designers to understand complex clock structure in the design and performs netlist and physical optimization. TimingExplorer helps designers to diagnose their timing problems and provides fix solutions. LibExplorer helps designers to analyze their timing libraries and analyze the RC characteristics of design interconnects
ICExplorer is Open Access based and it has various built-in physical design engines such placement, routing, static timing analysis, and parasitic extraction. All engines share common data model OpenAccess1. ICExplorer can be easily plugged into physical design flow since major data exchange formats such as Verilog, LEF, DEF and SPEF are supported. Figure 1 illustrates the architecture of ICExplorer.
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Figure 1 ICExplorer Architecture and Product Family
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ICExplorer Product Family
- DBExplorer is a physical design database management and data analysis platform. It hyper-links design data that it is really easy to do cross probing among data domains of layout, netlist hierarchy, gate level Verilog, SDC, connectivity schematic, and clock schematics.
- ClockExplorer is a comprehensive clock design environment which has major features:
- ClockAnalyzer is for clock structure analysis and constraint generation. Its functionalities include clock schematic creation, structure analysis, constraint verification, clock constraint generation, and design constraint merging. It merges multi-mode clock relation graph and generate clock tree synthesis sequence.
- ClockNetOpt is for clock gating topology optimization.
- ClockPhyOpt for clock skew and insertion delay optimization during physical design.
- TimingExplorer enables designers to diagnose their timing problems and provides fix solutions. The following are the list of major features of TimingExplorer:
- Browse and analyze MCMM design timing reports. Narrow down the timing violation cause. TimingExplorer can be used as a pure timing report analyzer
- Automatically identify the timing violation cause, provide solutions, and write out ECO scripts for third party implementation flows
- Provide extensive timing path inspection, design object analysis, and interactive what-if analysis utilities for user to manually search timing violation cause and find solutions.
- Enable user to simulate the impact of timing fix solutions in TimingExplorer which reduce the number of iterations to third party implementation tools.
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LibExplorer enables user to explore their timing libraries and RC characteristics of interconnect. This tool is built to be handy or easy to use. It has the look and feel of a scientific calculator.
LibExplorer requires two major types of input files, the timing library files and process technology files for interconnect.
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RCExplorer is the RC extraction tool for deep sub-micron IC Designs. In supports
both interactive and batch mode 3-D parasitic extraction. It
supports advanced technolgy such as 40nm and iPDK. It takes LEF/DEF, GDS, and OA as inputs.
It can be easily plugged into third party layout tools.
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