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Physical verification, as the gateway to manufacturing is the last phase in an IC implementation flow prior to tape-out. Since the cost of manufaturing an IC is high, its layout has to be thoroughly checked against a set of design rules to ensure manufacturability. Extensive physical verification runs are performed during implementation ("in-design" application) against a set of design rules. The final full-chip verification, referred to as "sign-off" run is exhaustive and is performed to make sure the design meets all design and manufaturing aware rules. Accuracy and speed are two required features for all DRC tools, and Argus has consistently shown to meet foundry needs in accuracy, and deliver performance comparable to sign-off DRC tools.


The SoC Verification solution is made up of ArgusTM for DRC/LVS, AetherTM for schematic/layout veiewing and editing, PVETM for DRC/LVS debugging, RCExplorerTM for interconnect analysis including pin-to-pin and point-to-point analyses. The solution fits equally well into existing 3rd party schematic/layout driven flows. 

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