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Qualib is a library/IP QA and debugging platform. Qualib aims at checking the consistency of all kinds of library files, and also the functionalities for debugging, cross-reference and reports generation. Currently, Qualib supports multiple formats including LEF, GDS, Timing Lib, Verilog and CDL. 


Key Features:

  • A comprehensive platform to qualify standard cells & IPs
  • Powerful interactive debugging functions for the source of problems
  • Advanced analysis features for better standard cell & IP quality
  • Flexible usage model and comprehensive reports


Benefits for IP users:

  • Find tape-out show stoppers earlier in the design cycle
  • Reduce risk of panic right before tape-out on issues not relevant to design
  • Enable design team with robust building blocks earlier in design cycle
  • Reduce risk of missing tape-out schedule


Benefits for IP creators:

  • Free customers from issues caused by IPs and let them focus on their own designs
  • Provide high quality IPs customers can trust



Ease of use:

  • Qualib provides both graphic and TCL based user interface
  • Comprehensive and easy to configure check list
  • Ping point problematic area for easy debug
  • User can see both GDS and LEF views for easy comparison
  • Provide both graphical and HTML/text based check/comparison reports



Customers' Words


"Using ICScape's physically-aware TimingExplorerTM and SkipperTM we reduced the number of timing closure iterations by at least 50% and clock tree power by almost 40% for a multimedia chip."

- Yu Xia, Sr. Physical Design Manager

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