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Quote from HiSilicon

"Practically speaking, every SOC design closure takes not only a significant amount of time and effort, but multiple iterations as well. Using ICScape’s physically-aware timing tool TimingExplorer™, and Skipper™, their chip finishing capability, we reduced the number of iterations by at least 50% on each SOC design. And we have reduced clock tree power by almost 40% in one of multimedia chip using optimized clock constraints generated fromClockExplorer." 

- Yu Xia, Senior Physical Design Manager

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