ICScape - Accelerate Design Closure

ICScape

ICScape is a technology leader, delivering fast, placement and ROUTING-aware design closure and optimization solutions addressing timing, clock and power in the design of SOCs. 

Why does SoC timing closure:       

• Take more iterations than desired?
• Result in ECO fixes that are not implementable?
• Lead to over buffering, or forced acceptance of lower chip performance?

Some of the main reasons are:   

• Poor timing correlation: STA and P&R tools
• P&R tools can handle only few MMMC scenarios per run
• STA-driven ECO is not ROUTING aware

Use TimingExplorer^TM which is:        

• Congestion and ROUTING-aware
• Simultaneously handles all MMMC scenarios
• Production-proven down to 28nm
• Over 100 tape-outs      

For more information go to TimingExplorer